Press Room

11/02/11 Shawn McCloud Joins Calypto as VP of Marketing to Support Company Focus on High-Level Synthesis and ESL Hardware Design

10/12/11 Greg Orzech Joins Calypto as VP of Worldwide Sales, Supports Company Focus on ESL Hardware Design

07/20/11 Calypto Joins ARM Connected Community: Verification and power optimization platforms for electronic design improve design quality, reduce power consumption (Japanese version)

06/02/11 Mentor Graphics Addresses 28nm and 3D-IC Requirements in TSMC Reference Flow 12

06/02/11 Calypto Announces Breakthrough Formal Verification Technology with Latest SLEC release: SLEC 6.0 improves runtime performance by 5X; enhanced support for HLS flows

05/26/11 Calypto Launches Indusrty's Most Advanced RTL Power Optimization Platform: PowerPro 5.0 deploys unique sequetnial optimization techniques and RTL power analysis for SoC power reduction; Improves runtime by 2X (Japanese version)

05/25/11 Real Intent and Calypto Partner to Offer Best-in-Class Integrated Tool Flow for RTL Power Optimization and Sign-Off

02/28/11 Media Alert: Calypto Design Systems to Exhibit its Power Optimization and Functional Verification tools at DVCon

01/27/11 Media Alert: Calypto Design Systems to Exhibit at EDSF

01/26/11 Calypto Prepares for Next Phase of Growth with New Chief Executive Appointment: Appoints Doug Aitelli as New CEO, Tom Sandoval to remain on Board of Directors

01/18/11 Calypto Extends Power Optimization Capabilities with PowerPro 4.1: 5X runtime improvements; added support for VHDL designs (Japanese version)

01/10/11 Calypto Reduces Runtime by 6X with Release of SLEC 5.1: Groundbreaking verification and modeling techniques dramatically improve design team efficiency

11/09/10 Media Alert: Calypto Design Systems Demonstrates Advanced Power Optimization and Functional Verification Tools at the ARM Technology Conference

10/06/10 STARC, Calypto and Virage Receive Editor’s Choice Award from Embedded Computing Design: Flow to reduce dynamic and leakage power in SoCs for 40nm and below Highlighted in ‘Deep Green’ Section (Japanese version)

08/30/10 Advantest Selects Calypto’s Power Optimization and Verification Tools to Reduce Power in ASIC Designs: PowerPro CG and SLEC Pro reduce dynamic power; improve design turnaround time for ASICs

08/24/10 STARC, Calypto and Virage Logic Break New Ground with Industry’s Lowest Power Design Flow: Partnership enables complete, seamless flow to reduce dynamic and leakage power in SoCs for 40nm and below (Japanese version)

06/25/10 Media Advisory/Alert: Calypto Design Systems and AST to Sponsor
Power Aware Design Seminar

06/09/10 Calypto’s Power Optimization Platform Adopted by Ikanos for SoC Power Optimization: PowerPro CG and PowerPro MG along with SLEC Pro Deliver the Industry’s Only Complete RTL Power Optimization and Comprehensive Verification Solution (Japanese version)

06/08/10 Calypto Extends Industry Lead in RTL Power Optimization: Mode-Based Design Optimization, Enhanced Usability Features Further
Reduce Power and Improve Design Team Efficiency (Japanese version)

06/07/10 Calypto Expands Industry Lead in ESL Verification with
Latest SLEC Release: New Breakthrough in Formal Verification Technology for Complex Loop Handling  (Japanese version)

04/26/10 Calypto Names Innotech its Exclusive Distributor in Japan: Extends Calypto’s Reach in the Global Electronics Market (Japanese version)

04/12/10 STARC Adopts Calypto’s PowerPro® MG in their STARCAD-CEL Version 4.0 Design Flow: Consortium’s Evaluation Demonstrates over 40 Percent Reduction in Memories’ Dynamic Power Using PowerPro MG (Japanese version)

02/22/10 Calypto’s PowerPro MG Named a Finalist in 20th Annual EDN Innovation Awards: A prestigious honor for the industry’s only automated memory power optimization tool

02/01/10 Virage Logic’s 45nm and 28nm SiWare Memory Compilers Automatically Support Calypto’s PowerPro MG tool; Compilers automatically generate PowerPro MG views to fully automate on-chip memory power optimization (Japanese version)

01/19/10 Calypto Broadens Industry’s Most Comprehensive Power Optimization Product Family with New PowerAdviser Flow: Leverages sequential analysis technology to deliver most complete RTL power optimization solution (Japanese version)

12/16/09 Calypto’s PowerPro MG Named ‘Best of 2009’ by Electronic Design (Japanese version)

11/23/09 Calypto Empowers Intrinsity to Deliver Industry’s Fastest, Most Power-efficient Third-party Processor Cores: Comprehensive Verification Tool Enables Intrinsity to Aggressively Optimize Designs  

08/24/09 Calypto Delivers Industry’s First RTL Power Analyzer Based on Sequential Analysis Technology: Achieves RTL-level Power Analysis Results with Gate-level-like Accuracy in a Fraction of the Time

07/27/09 Calypto Delivers Fully Automated Sequential Optimization Flow for High-performance IP Blocks: PowerPro CG, SLEC RTL Combine with Popular Synthesis Tools to Achieve Power, Performance and Area Goals

07/20/09 Calypto Enables ESL Design and Verification of Complex Designs with 5x Capacity Improvement: Improves HLS Tool Integration to Boost Designer Productivity, Adds Multiple Clock Support

06/22/09 Calypto Delivers Industry’s First Automated Tool for Memory Power Optimization: PowerPro™ MG Enables system-on-a-chip (SoC) designers to produce the lowest power memory implementation possible (Japanese version)

06/09/09 Calypto Delivers 'Picture Perfect' ESL Solution to Casio: Calypto Teams with Cadence Design Systems to Improve Design Efficiency, Speed Time-to-Market of Digital Cameras (Japanese Version)

01/21/09 ARC, Calypto Team to Reduce Power in ARC's Video Subsystem Solution: Calypto's PowerPro CG Reduces Power by 15% on Previously Optimized Design (Japanese Version)

11/10/08 Calypto Announces New SLEC Release for Comprehensive Verification of Wireless, Video, Image Processing System-on-Chip Designs: Latest Capabilities Support Fixed-Point Datatypes, System-Level Memory Interfaces (Japanese Version)

10/27/08 Calypto's PowerPro CG Cuts Power Consumption in Pixim's Latest Video Image Processor: Silicon Proven, Power Savings Achieved with No Impact to Project Schedule

10/22/08 Calypto, Forte Collaboration Results in Advanced SystemC Design Flow: System-Level Design, Verification Solutions Provides Competitive Advantage for Consumer, Multimedia SoC Applications (Japanese Version)

10/20/08 Calypto Strengthens PowerPro CG with New Power Optimizations, VHDL Support: Extends Power Savings Benefits to European Consumer, Wireless Designers Using VHDL (Japanese Version)

08/04/08 Calypto’s PowerPro CG Selected by AMD to Reduce Power in Processor Designs: PowerPro CG Improves Performance Per Watt Under Peak Operating Conditions (Japanese Version)

07/14/08 Calypto's Sequential Equivalence Checking Product Supports New Cadence C-to-Silicon Compiler: SLEC System-HLS Offers Comprehensive Formal Verification for Algorithm-to-RTL Equivalency Checking

07/08/08 Calypto Selects Saline as its Exclusive Distributor in Korea: PowerPro CG "Perfect Fit" for Korean Semiconductor Companies Focused on Power-Sensitive Consumer Markets

05/23/08 Calypto Delivers Optimized Power Flow with Cadence Design Systems: Power optimization flow reduces power consumption without compromising performance

05/21/08 Calypto to Offer Power Profiling Software Free of Charge at DAC: Calypto’s Power, Verification Experts to Demonstrate Products, Participate in DAC Technical Program

05/14/08 Calypto Names Maojet Exclusive Distributor in Taiwan: Extends Calypto's Reach in the Global Electronics Market

05/13/08 Calypto Selects AST Ltd. as Distributor, Technical Representative in Israel: Strong Demand for Calypto Products Drives Move into Israel

05/07/08 Calypto Completes Another Successful Financial Year with Record Bookings: Revenue More than Doubles Year to Year as Customer Base Expands Worldwide

03/24/08 Calypto Releases PowerPro CG 2.0: Additional Power Savings,Graphical Power Analyzer Broaden PowerPro CG’s Application for Storage, Processor Markets

02/18/08 STARC Reduces SoC Design Power with Calypto’s Unique PowerPro CG Product (Japanese Version)

07/18/07 Calypto Names Doug Aitelli as Vice President of Worldwide Sale

05/22/07 Calypto Doubles Revenues and Expands Customer Base as New Products Set Stage for Continued Growth

03/26/07 Calypto Debuts Sequential Power Optimization Solution for Automated RTL Power Reduction (Japanese Version)

03/14/07 Calypto's SLEC™ RTL Product Selected by AMD to Verify Advanced Processors

11/6/06 Calypto Extends Capabilities with Launch of SLEC CG for Verification of RTL Power Optimizations

10/30/06 Calypto Expands India Operations, Names Local Area Distributor

09/25/06 Calypto Design Systems Expands European Presence

05/22/06 Calypto Expands Sequential Analysis Capabilities with SLEC 2.0 Release

01/27/06 Calypto Transitions to Next Stage of Growth with Addition of Tom Sandoval as CEO

10/03/05 Calypto and Forte Collaborate on Formal Verification and Behavioral Synthesis Tool Integration

08/10/05 Calypto Continues Focus on Technology Leadership with Appointments of New Technology Advisory Board Members

06/10/05 Calypto SLEC Sequential Equivalence Checker Deployed By Freescale Semiconductor PC owerPTeam

06/02/05 Calypto and Mentor Graphics Integrate Tools for Verifiable, Automated Path from System to RTL

04/25/05 Calypto Pioneers Breakthrough Verification Technology

02/01/05 Calypto Design Systems Expands Presence in Japan

01/17/05 Calypto Design Systems Reveals Strategy To Bridge System and RTL Design