ESL Synthesis
Catapult C Synthesis
  • Catapult C Synthesis is a high-level synthesis tool for ASIC and FPGA hardware designers who need to deliver optimal implementations with aggressive time-to-market requirements.
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Functional Verification
  • The industry's only proven Sequential Logic Equivalence Checker
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SLEC System
  • SLEC System verifies RTL designs and system-level models without testbenches or assertions.
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SLEC System-HLS
  • SLEC System-HLS comprehensively verifies the RTL generated by High Level Synthesis (HLS) tools.
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SLEC RTL
  • SLEC RTL allows designers to confidently make complex power and performance optimizations.
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SLEC Pro
Power Optimization
PowerPro CG
PowerPro MG
PowerPro Analyzer
PowerAdviser Flow
  • Ensures designs are power optimized to the fullest extent.
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