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White Papers
Integrating Sequential Logic Equivalence Checking with the Cadence C-to-Silicon Flow
High Level Synthesis (HLS) tools are well entrenched in consumer product companies who want to get from algorithm to silicon in a relatively short span. Today, HLS tools are not only being used to generate RTL descriptions but also to perform architectural exploration of the design, reduce verification time and create reusable IP. This white paper talks about integrating sequential logic equivalence checking with high-level synthesis to improve productivity and confidence in the ESL design flow. Specific emphasis is placed on the integration between SLEC and Cadence CtoSilicon Compiler (CtoS).
PowerAdviser: Empowering Designers with Sequential Power Optimization Opportunities
In power-sensitive products, SoC designers may spend a significant portion of their time looking for ways to optimize their code to dissipate less power during the device’s operation. PowerProCG provides an automated solution to reduce this part of the design time to essentially cut it down to just machine runtime per block. In this paper, we describe a flow that enables two use models; one is to enable the use of PowerPro for designers who must meet very aggressive performance goals and would therefore prefer to optimize their RTL manually, and the other is to enable users of the automated PowerProCG flows to get even better results by providing hints based on sequential analysis. This flow, available within the PowerPro product, is known as PowerAdviser.
Memory Power Reduction in SoC Designs Using
PowerPro MG
Memories occupy over 50% of the silicon real estate on most modern SoCs and account for 50-70% of the power dissipation. As such, selecting the optimal memory architecture and ensuring that the memories are controlled to optimize memory accesses is critical to meeting the overall SoC power budget. With power becoming a critical design consideration, memory vendors have been providing more power efficient memory architectures and power modes in their memory IP to enable SoC designers to use power reduction techniques such as sleep modes and dynamic voltage and frequency scaling. Exploiting sleep modes in memories and identifying scenarios where memories may be read or written redundantly requires designers to analyze the memory and the surrounding logic across multiple cycles. In this paper, we survey the key power reduction techniques available in memories designed for 40 and 32 nm process nodes from Virage Logic. We will show how Calypto’s PowerPro MG tool can significantly reduce the dynamic and leakage power consumption in memories by automatically inserting new memory gating logic to remove redundant reads/writes and control the sleep modes available in these memories.
Power Optimization of a Configurable Video Platform using PowerPro™ CG
With the proliferation of mobile multimedia devices, designers are challenged to provide the most advanced features to users while balancing the need to deliver the longest battery life possible. Maintaining this balance has been a significant challenge for designers, with no automated solutions available to ensure the lowest power solution is achieved. One way to reduce power and extend battery life is to reduce the amount of switching activity in the device. Understanding how the silicon works in normal use can help direct subsystem design changes to eliminate unnecessary switching activity without sacrificing leading edge functionality and performance. Once identified, the challenge is to quickly and efficiently implement the changes in the RTL and be able to verify that the functionality has not been affected by the changes.
Today, most ICs designs include the integration of newly designed circuitry, legacy circuitry available from a previous design generation, and 3rd party IP. Realizing the lowest power design while integrating legacy circuitry and 3rd party IP is extremely difficult. Without the detailed knowledge of how the RTL works, most designers choose to concentrate their efforts on optimizing power on the newly designed circuitry, ignoring the additional power savings that could be achieved on the other portions of the design.
Making the Move to ESL Hardware Design
Electronic system level (ESL) is typically defined as design above the register transfer level (RTL). When applied to hardware design, ESL is the process of describing hardware functionality at higher levels of abstraction to increase designer productivity and enable greater degrees of exploration. With ESL, hardware designers no longer spend most of their time designing and verifying RTL code.
This seems straightforward, but ESL hardware design presents engineers with a set of noteworthy challenges. These include learning new languages, understanding how to produce quality RTL implementations from system-level code and successfully introducing new EDA tools into the design flow.
That said, ESL has now been around for more than 10 years, more and more semiconductor companies are using ESL tools, and consequently ESL methodologies rapidly maturing.
This paper illustrates that increasing maturity by describing a system level-to-RTL design flow. It looks at the issues involved in switching to ESL hardware design and provides insights into some of the appropriate design and verification tools.
Automating Sequential Clock Gating
Clock gating is a common Register Transfer Level (RTL) power optimization. Today, RTL synthesis tools identify and automate simple, combinational clock gating. However, greater power savings can be achieved through sequential clock gating optimizations. Until recently, sequential clock gating required manual identification and implementation by expert hardware designers. Now, with the availability of RTL power optimization tools, designers have access to advanced automated, low-power design techniques, eliminating the need for the often difficult and error-prone manual methods.
This article describes sequential analysis and its application to clock gating. An example of sequential clock gating is given as well as a case study of reducing power in a digital signal correlation block using an automated RTL power optimization tool.
Leveraging System Models for RTL Functional Verification using Sequential Logic Equivalence Checking
RTL verification remains the bottleneck in digital hardware design. Industry surveys show that functional verification accounts for 70% of the total design effort. Yet despite the emphasis on verification, over 60% of all design tape-outs require a re-spin [1]. The predominated cause for re-spins is logic or functional flaws. That is, defects that could have been caught by functional verification. Clearly improved verification techniques are needed.
Design teams commonly use system models for verification. System models have many advantages over RTL for verification, namely ease of development and runtime performance. The challenge is bridging the gap between system-level verification and creating functionally correct RTL. Sequential Logic Equivalence Checking (SLEC) has the unique capability to bridge this gap by formally verifying RTL implementations against a specification written in C/C++ or SystemC.
Sequential Equivalence Checking: A new approach to functional verification of datapath and control logic changes
This paper discusses the effect of sequential changes on functional verification. Sequential transformations are typically done at the system-level and RTL design to improve power, timing and area. Several sequential transformations to datapath and control logic are shown. Sequential changes are avoided late in the design process because of their impact on functional verification. Consequently, designers tend to favor datapath and control logic modifications that least disturbs testbenches. However "verification limited design" ties the hands of engineers and sometimes sequential changes cannot be avoided. This paper introduces a novel solution, sequential equivalence checking, as well as suggestions to improve testbench robustness to minimize impact of sequential changes on functional verification.
The Power of RTL Clock Gating
To effectively reduce dynamic power, hardware designers must understand a multitude of clock gating transformations and have the practical experience to know when they should be applied. The tradeoff between power reduction and verification cost is not always clear so designers tend to be cautious, leaving power savings on the table. That is, until they don't have a choice.
Utilizing Clock-Gating Efficiency to Reduce Power in RTL Designs
With the advent of the consumer era and the popularity of mobile applications, power optimization is the mantra of the day. Designers go through several iterations to optimize power in order to achieve their power budgets. Though power should be optimized at all stages of the design flow, optimizations in early design stages have the greatest impact in reducing power.
RTL Clock Gating is the most commonly used optimization technique for reducing dynamic power. The challenge of optimizing power by adding clock gating is knowing where and when to insert clock gating. The traditional method of looking at the percentage of registers that are clock gated is not indicative of the power savings because it does not take into account switching activity. The average Clock-Gating Efficiency for a design is a much better indicator of dynamic power consumption because it is a measure of both how many and how long registers are gated.
Navigating the System to RTL Continuum
The rapidly evolving semiconductor industry has always relied on innovation to sustain advancement. From the creative forces behind the myriad of consumer electronic products to the technology improvement behind sub-micron silicon running at gigahertz speed, innovation makes electronic systems possible.
Gartner Dataquest (2004) states that more than half of IC designs are System-on-Chip (SOCs) meaning they contain some type of processor and memory subsystem. With the adoption of IP, from internal or external sources, additional importance is placed on system-level design and integration. Designers are being pushed to work at higher levels of abstraction while at the same time meet strict power and performance requirements. In addition to these pressures, design teams are faced with the familiar challenge of getting their SOC working within a tight project schedule.
It is clear that the semiconductor industry must adopt system-level design and verification methodologies. However, before design teams can move forward there is a prerequisite on tools and technologies that support a RTL to system level transition.
Verification Without Testbenches
Increasingly, designers begin with high-level models to partition and verify system functionality. Best-practicing teams reuse these models within testbenches to verify the resulting RTL designs. However, the cost and brittleness of these testbenches limit the design team's ability to explore and optimize their RTL. Sequential equivalence checking technology reduces testbench requirements, improving productivity and giving designers more opportunities to optimize their RTL designs. This paper traces the development of a DES encryption design to demonstrate the advantages of doing RTL verification without testbenches.
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