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Benefits of SLEC Pro

  • Comprehensive verification of PowerPro results
  • 100% test coverage of all clock gating enable conditions
  • Integrated flow with PowerPro to improve verification productivity
  • Eliminates the need for clock gating specific testbench development
  • Replaces time consuming simulation regressions with fast results
  • Isolates bugs quickly with short, concise debug waveforms

SLEC Pro formally verifies PowerPro power optimizations.

Based on Calypto's patented Sequential Analysis Technology, SLEC Pro provides efficient, comprehensive verification of PowerPro optimized RTL.

SLEC Pro formally compares the functionality of the original RTL design with the PowerPro optimized RTL design for all possible input sequences. Unlike combinational equivalence checkers, SLEC Pro does not require one to one mapping of registers.

SLEC Pro confirms that no functional errors exist in any of the clock-gating enable conditions added or modified by PowerPro or generates short, concise waveforms that pinpoint design differences. These waveforms are written in standard VCD and FSDB formats that can be analyzed in the user's native debugging environment.

SLEC Pro is seamlessly integrated into the PowerPro design flow to remove the need for users to specify design files and setup.

SLEC Pro is part of Calypto's SLEC family of proven sequential equivalence checking products.