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Benefits of SLEC RTL

  • Uncovers functional errors that are difficult to detect in simulation
  • Reduces the design effort required to meet timing
  • Verification without writing testbenches and assertions
  • Replaces time consuming simulation regressions with fast results
  • Isolates bugs quickly with short, concise debug waveforms

SLEC RTL allows designers to confidently make complex power and performance optimizations.

Based on Calypto’s patented Sequential Analysis Technology, SLEC RTL functionally verifies RTL optimizations such as retiming and clock gating.

SLEC RTL finds design errors that other tools miss by formally comparing the functionality of the original RTL design and the corresponding optimized RTL design for all possible input sequences. Unlike combinational equivalence checkers, SLEC RTL does not require one to one mapping of registers.

SLEC RTL either confirms that no functional errors exist or generates short, concise waveforms that pinpoint design bugs. These waveforms are written in standard VCD and FSDB formats that can be analyzed in the user’s native debugging environment.

SLEC RTL is part of Calypto’s SLEC family of proven sequential equivalence checking products. SLEC RTL includes the functionality of SLEC Pro.