Calypto in the News

06/12/11 Low Power Design - Need to Cut IP Power? (Who doesn't) "Press Here" says Calypto

06/06/11 EETimes - DAC 360 Video Interview: Calypto Announces Extensions of PowerPro Software Tool

06/06/11 EDA Cafe - Concept Engineering's Nlview Visualization Engine Adopted by Calypto Design Systems to Power the Debugging GUI of PowerPro Product Family

06/02/11 DeepChip - My Cheesy Must See at DAC 2011 List

06/02/11 EDA Cafe - Calypto Announces Breakthrough Formal Verification Technology with Latest SLEC Release

05/28/11 Chip Estimate - Calypto Launches Industry's Most Advanced RTL Power Optimization Platform

05/27/11 EETimes Europe - RTL Power Optimization Platform Improves Runtime by Factor of 2

01/26/11 EETimes - EDA Firm Calypto Names New CEO

01/18/11 SOC Central - Calypto Extends Power Optimization Capabilities with PowerPro 4.1

01/10/11 SOC Central - Calypto Reduces Runtime by 6X with Release of SLEC 5.1

10/21/10 Chip Design - The Growing Need for Concurrent Design

09/16/10 Embedded Computing Design - Green In: Power-saving DSP Core, Noise-adapting PLC Chip, and a Low-power EDA Design Flow

09/02/10 Calypto CEO Interview: Why System Realization Needs Sequential Analysis

05/03/10 - Powering Down: Enabling a Power Regression Flow for SoC Design

01/19/10 Chip Design - Calypto PowerAdviser Flow Optimizes SoCs

01/19/10 EDN - Calypto to Power-management Experts: Have it your way

12/01/09 Electronic Design - ESL Tools Take Center Stage as Designers Move Up

10/15/09 Low-Power Engineering - Considerations for Choosing the Right Low-Power Tools

10/15/09 EDA DesignLine - How to Reduce Memory Power in SoC Designs

09/17/09 EDA DesignLine - Verification Alive and Well at SoC Virtual Conference

08/11/09 Chip Design -Verification Vertigo Blog- Interview with Tom Sandoval, CEO of Calypto

08/01/09 Low-Power Design - Squeezing Excess Power Out of Synthesized Blocks

07/27/09 EDA Blog - Calypto Sequential Optimization Flow

07/27/09 EE Times - Calypto offers full design flow for SoC IP blocks

06/25/09 Electronic Design - Tool Automates Power Optimization of Embedded SoC Memories

06/22/09 EE Times - Calypto tool lets SoC designers reduce memory power

06/22/09 EDN - Calypto Delivers Industry’s First Automated Tool for Memory Power Optimization

06/09/09 EDA Cafe - Calypto Delivers 'Picture Perfect' ESL Solution to Casio

05/29/09 SCDsource - Special Technology Report: Mixing Formal and Dynamic Verification, Part 2

05/26/09 EDA Design Line - Minimizing Power Consumption in RTL Designs Using Sequential Clock Gating and Low-Power Synthesis

03/25/09 EDA Confidential - Reaching the EDA Customer

03/07/09 EDA Cafe - Is EDA History? Is it Doomed?

01/23/09 SOCcentral - ARC, Calypto Team to Reduce Power in ARC's Video Subsystem Solution

01/15/09 DACeZine -Leveraging System Models for RTL Functional Verification using Sequential Logic Equivalence Checking

01/12/09 EDA Cafe - Sequential Analysis

12/24/08 EDA DesignLine - Top Design Articles for 2008

12/16/08 SCD Source - Ten 2009 Trends in System and Chip Design

11/25/08 Portable Design - Reducing Power in Video-Intensive Portable Applications

11/10/08 EDA Design Line - Calypto Announces New SLEC Release

10/20/08 EETimes - Calypto Adds VHDL Support to PowerPro CG

09/09/08 EDA Design Line - Reducing Power Consumption in a Fiber Channel Switch

08/05/08 SOCcentral - Formal Verification Goes Mainstream

08/01/08 EDA DesignLine - The Power of Sequential Design Optimizations

07/14/08 EETimes - Cadence Introduces C-to-Silicon Compiler

07/14/08 SCDSource - Cadence Claims 'Next Generation' High-level Synthesis

07/14/08 EDN - Practical Chip Design: Cadence C-to-Silicon Synthesis May Mark Next Round in ESL Tools

06/30/08 EETimes - Are IC Thermal Problems Hot Air?

06/26/08 DACeZine - Facing Down the Perfect Storm

06/09/08 STMicroelectronics Announces Certified Design Flow to Accelerate Creation of Next-Generation Silicon

06/05/08 Portable Design - Calypto and Cadence Deliver Optimized Power Flow

05/12/08 SOCcentral - ESL Is Finally Ready for Prime Time

04/01/08 DACeZine - Innovation in EDA

04/01/08 IC Design & Verification Journal - Attacking Abuses of Power - Part 2

03/24/08 SOC Central - Calypto Releases PowerPro CG 2.0 

02/19/08 IC Design & Verification Journal - Attacking Abuses of Power - Part 1

02/11/08 EETimes - Hardware Design Using ESL

01/15/08 EDN - Between the Lines: Calypto RTL to ESL Equivalence Checker gets Vote of Confidence

01/15/08 EDA DesignLine - Utilizing Clock-Gating Efficiency to Reduce Power

01/14/08 SCDSource - Sequential Equivalence Checker Supports C Synthesis Tools

01/06/08 Portable Design - Designing Energy-Efficient Consumer Electronics

12/14/07 EDN - EDN Hot 100 Products of 2007

12/03/07 EETimes - Leveraging System Models for RTL Functional Verification

11/05/07 Electronic Design - Stanch The Bleeding Of Leakage Power At 65 nm

10/19/07 EETimes - Viewpoint: RTL-ers should move to ESL

10/05/07 Design and Reuse - How effective use of ESL tools can increase your HW/SW system design productivity

04/10/07 EETimes - Calypto power optimizer supports CPF

03/26/07 EETimes - Power tool taps clock gating

03/14/07 SOCcentral - Calypto's SLEC™ RTL Product Selected by AMD to Verify Advanced Processors

01/26/07 EE Times - Models hold value, not IP

01/20/07 Chip Design/iDESIGN - The Power of RTL Clock-gating

01/17/07 Electronic Design - Design Complexity Spurs The Need For Formal Verification

12/20/06 EE Times India - Calypto hosts seminar on ESL methods for RTL design

11/06/06 EE Times - Calypto equivalence checker eyes clock gating

10/30/06 EE Times - Larger EDA vendors are finally realizing the time for offering real ESL solutions is longoverdue

09/04/06 EDA Cafe - Tom Sandoval's Top Ten Catechisms for Venture Capital Success

08/18/06 EDACafe - Calypto - Equivalence Checking

06/22/06 Electronic Design - Sequential-Logic Equivalence Checker Gains Capacity And Speeds Up Runtimes

06/19/06 EE Times - Sequential equivalence checking for RTL models

05/22/06 EE Times - Sequential logic equivalence checker claims huge speed boost

05/15/06 EE Times - Sequential equivalence checking supports ESL flow

03/24/06 SOC Central - Re-Timing Verification Using Sequential Equivalence Checking

01/27/06 EE Times - EE Times - Calypto names former LSI Logic exec CEO

12/07/05 EE Times - Calypto sees ESL take hold in U.S.

12/05/05 EDN - SLEC chosen as one of the top 100 products of 2005.

11/14/05 EE Times - Designing hardware with C-based languages

11/01/05 EE Times - EE Times updates list of 60 emerging startups

10/25/05 EE Times - The 2005 "verification census" survey recap

10/25/05 - 2005 Verification Census – Calypto SLEC

10/17/05 EE Times - ESL providers get practical

10/11/05 Nikkei Microdevices - Renesas Selects Sequential Equivalence Checker for Confidence in Functional Verification

10/07/05 Nikkei Microdevices - Sequential Equivalence Checker accelerates C based design

10/05/05 EDN Japan - New Equivalence Checker Verifies Functionality: Enables System to RTL Verification

10/04/05 SOC Central - Calypto and Forte Collaborate on Formal Verification and Behavioral Synthesis Tool Integration

10/04/05 Embedded Star - Calypto, Forte Integrate Formal Verification and Behavioral Synthesis

EE Times - Companies claim first integrated solution for SystemC users

10/03/05 EE Times - Verification moves to a higher level

10/01/05 DesignWave - Formal Verification tool covers SystemC

09/01/05 Electronique - Sequential Equivalence Analysis: Ready for System Level Design

09/01/05 Electronique - An Essential Brick for the Move to ESL (DAC Recap)

09/01/05 EDA Tech Forum - Verifying micro-architectural optimizations for high-performance system-on-chip designs

08/30/05 Elektronik Tidningens - New Interests for High Abstraction

08/10/05 EE Times - Startup Calypto Design Systems adds two to tech advisory board

08/01/05 Prosessori - Calypto – Novel Solution

07/01/05 Inside Chips - Calypto, Mentor Integrate Tools

06/29/05 - Industry Gadfly: Post-DAC Debriefing

06/21/05 Electronic Design - Launching Into the System-To-RTL Continuum

06/13/05 Kumikomi Networks - DAC 2005 Report

06/10/05 EE Times - Must See List for DAC 2005

06/09/05 - Industry Gadfly: Must See List For DAC 2005

06/06/05 SOC Central - Don't Forget the Little Guys!

06/02/05 EE Times - Startup integrates equivalence checker with Mentor's Catapult

06/02/05 SOC Central - Calypto and Mentor Graphics Integrate Tools for Verifiable, Automated Path from System to RTL

05/31/05 SOC Central - The Open SystemC Initiative and OCP-IP Join Forces to Target TLM Layer Standardization

05/12/05 Electronique International Hebdo - Verifier l'equivalence entre implantation RTL et specification systeme

05/12/05 Electronic Design - Equivalence Checker Handles Sequential Logic

05/01/05 Electronic Products News - EDA Movie: DATE 2005

05/01/05 Elettronica Oggi - Mondo Elettronico

05/01/05 Inside Chips - Calypto Launches Industry's First Sequential Equivalence Checker

04/26/05 Embedded Star - Calypto Rolls Out SLEC Sequential Logic Equivalence Checking Solution

04/25/05 Electronics Weekly - Formal Analysis at the System Level

04/25/05 EE Times - Startup preps for ESL design

04/25/05 EE Times - New verification tools intended to bridge system-level with RTL

04/25/05 EDN - EDA startup brings formal analysis to the system level

04/24/05 Hindustan Times - IIT Delhi displays R&D power to industry titans

03/25/05 Electronic News - Design at the System Level

03/17/05 Electronic News - Design at the System Level

03/17/05 Electronique - Le nanometrique impose une evolution des methodologies de conception

03/08/05 Electronic Design - Dispatch from DATE 2005

03/01/05 Inside Chips - Emerging Ventures

02/04/05 Nikkei Microelectronics - Calypto to Reduce ASIC Development Time Through Capability to Verify Equivalence Between SystemC and RTL

02/01/05 Chip Design - People

01/27/05 EDA Nation - Citizenry

01/24/05 EE Times - Startup paves way for ESL jump

01/19/05 EE Times Asia - EDA startup preps sequential equivalency checker

01/18/05 Electronics Talk - Calypto readies its design portfolio


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