Calypto Quarterly Newsletter

Calypto Newsletter

June 2010 Issue

Message from the Chief Executive Officer

Welcome to the DAC 2010 issue of the Calypto Newsletter. I hope you find the attached articles and links useful in learning more about Calypto’s unique solutions for sequential logic equivalence checking and RTL power optimization. 

Calypto once again had record financial results for our 2010 fiscal year (ended April 30) including 70% bookings growth over our 2009 fiscal year.  This growth was driven by the increased adoption of our SLEC product in the ESL space and the continued success of our PowerPro family of products.

In April, we announced that STARC, a research consortium co-founded by major Japanese semiconductor companies, had adopted our PowerPro MG for their latest SoC design flow.  PowerPro MG surpassed STARC’s initial goal to reduce dynamic memory power by 10 percent, delivering a reduction of over 40 percent.  PowerPro MG also delivered over 60 percent memory leakage power reduction by using a low leakage power mode called light sleep which is enabled using a single pin.  In both cases, SLEC Pro was then used to verify comprehensive equivalence between the original RTL design and the PowerPro MG optimized RTL design. 


What's New in SLEC®5.0

SLEC® version 5.0 was released on May 31, 2010. The latest version of SLEC contains the following features and enhancements:

  • Next generation formal verification algorithms to handle designs with deep, complex loops which dramatically improve the user experience and deliver a comprehensive and scalable verification solution for a broader set of design applications.
  • New techniques to model memories that reduce their size in SLEC’s database by up to 90 percent and effectively increase the size of the memories that can be handled by SLEC.
  • SLEC 5.0 includes enhanced flows for the three leading high level synthesis (HLS) products in the market, improving usability and expanding the support of their latest features:
    • For Mentor CatapultC:  New cat2SLEC flow auto-refines throughput, latency, ac_channel size, flop maps and reset length
    • For Cadence C-to-Silicon:  New ctos2SLEC flow that utilizes CtoSilicon XML database to auto populate design characteristics required for SLEC Verification
    • For Forte Cynthesizer:  New cyn2SLEC, fully automated support for external memories and custom interfaces in pipelined designs

These new capabilities further reinforce SLEC’s position as the cornerstone of today's advanced high-level synthesis (HLS) design flows. Users should move to SLEC 5.0 as soon as possible.

Calypto in the News

05/03/10 - Powering Down: Enabling a Power Regression Flow for SoC Design

02/22/10 Calypto’s PowerPro MG Named a Finalist in 20th Annual EDN Innovation Awards: A prestigious honor for the industry’s only automated memory power optimization tool

02/01/10 Virage Logic’s 45nm and 28nm SiWare Memory Compilers Automatically Support Calypto’s PowerPro MG tool; Compilers automatically generate PowerPro MG views to fully automate on-chip memory power optimization (Japanese version)

01/19/10 Chip Design - Calypto PowerAdviser Flow Optimizes SoCs

01/19/10 EDN - Calypto to power-management experts: have it your way

12/16/09 Calypto’s PowerPro MG Named ‘Best of 2009’ by Electronic Design (Japanese version)

12/01/09 Electronic Design - ESL Tools Take Center Stage as Designers Move Up


PowerPro® Tips & Tricks

Bottom Up Flow Methodology

PowerPro CG provides a fully automated approach to reducing power at the RTL level.  Because designs today are generally partitioned into functional hierarchies that can enable more efficient flows, Calypto has ensured that PowerPro CG has all the required features to fit directly into a hierarchical approach to RTL design optimization.  This enables more efficient use of licenses and also allows PowerPro to be used on very large designs.

Consider the following structure of block identified for PowerPro.


Now, let’s assume that PowerPro will be run hierarchically on “Block1” and “Block2” respectively and that the power optimized design will be re-assembled in the context of “Core”.  Consider that module “B” gets optimized differently as a part of PowerPro runs on “Block1” and “Block2”.  This commonly occurs in blocks that are duplicated in a design since the optimizations performed by PowerPro CG are in-context. 

This is where a Bottom-Up Flow Methodology will help the design team to optimize the “Core” design with minimal manual effort. The question here is, “How to resolve file/package/library name conflicts while stitching files generated from PowerPro runs on sub-blocks?”


Run each sub-block with the following modifications to the standard PowerPro run file.

set TOP Block1
build_design –top $TOP –f  top.f
config_write_rtl                                                                                          \
  -rename_all_modified_modules       yes                                                   \
  -separate_uniquified_module_files  yes                                                   \
  -uniquified_module_naming_scheme                                   ${TOP}_%s  \
  -observability_logic_module_naming_scheme             obs_${TOP}_%s  \
  -observability_logic_instance_naming_scheme        i_obs_${TOP}_%s  \
  -const_stability_logic_module_naming_scheme         cstb_${TOP}_%s  \
  -const_stability_logic_instance_naming_scheme    i_cstb_${TOP}_%s  \
  -sym_stability_logic_module_naming_scheme           sstb_${TOP}_%s  \
  -sym_stability_logic_instance_naming_scheme      i_sstb_${TOP}_%s  \
config_reset_spec  -location                                                           $TOP  \
                                 -reset_hier           ppro_reset_$TOP \
                                 -reset_instance i_ppro_reset_$TOP \

Merging the Optimized Files in Context of “Core”

To merge the files and generate a single filelist

  • Creating an absolute filelist

    sort –u */powerpro_rtl*/rtl_mod.f  > rtl_mod.f

  • Creating a relative filelist so that the directory can be copied

              cp –i */powerpro_rtl*/*.v merged_dir/

   sort –u */powerpro_rtl*/rtl_mod_rel.f > merged_dir/rtl_mod_rel.f

Please note that you are required to take the rtl_mod.f, rtl_mod_rel.f from the latest directory containing these files.

For instance, if one runs only Observability based optimization, one should pick these files from powerpro_rtl_insert_obs directory. If both Observability and Stability optimizations have been run and PowerPro found both types of optimizations, the directory to work with should be powerpro_rtl_insert_stb_s.

NOTE : The various stages of optimizations which are present in various RTL sub-directories are : powerpro_rtl_insert_<obs|stb_c|stb_s> in that order.

NOTE: Some manual intervention is required in case of VHDL designs as sorting can disrupt the original order of the files.

Product Information

PowerPro® MG
PowerPro MG is an automated memory power optimization solution that takes advantage of the low-power control options available in today’s on-chip memories to reduce both dynamic and leakage memory power with little or no impact to timing or area. PowerPro MG reduces dynamic power by automatically generating logic to control the memory enable signal to eliminate unnecessary memory accesses. 

PowerPro® CG
Based on Calypto’s patented Sequential Analysis Technology, PowerPro CG reduces power by up to 60% in RTL designs. PowerPro CG evaluates circuit behavior across multiple clock cycles to identify sequential clock gating enable conditions. New enable logic is inserted into the original RTL code while maintaining all user defined pragmas and comments.

PowerPro® Analyzer
PowerPro Analyzer is the industry’s most accurate register-transfer level (RTL) power analysis tool. PowerPro Analyzer performs sequential analysis of the entire design, delivering power measurement results that are significantly more accurate than the decade-old RTL power analysis tools in use today.

PowerAdviser Flow

The PowerAdviser Flow provides designers with a flow for manually modifying RTL code during design creation to achieve the lowest power dissipation possible using design and power information generated by PowerPro.


SLEC® System
Enabling ESL
SLEC System finds design errors that other tools miss by formally comparing the functionality of an Electronic System Level (ESL) model written in C/C++/SystemC with its corresponding RTL design or system-level model for all possible input sequences. Unlike combinational equivalence checkers, SLEC System does not require one to one mapping of registers. The quality of verification SLEC System performs in minutes is equal to months of running simulation.

SLEC® System-HLS
SLEC System-HLS finds design errors that other tools miss by formally comparing the functionality of a system level model written for HLS with its corresponding synthesized RTL design across all possible input sequences. SLEC System-HLS increases design productivity through automated setup and elimination of block-level RTL simulation.

SLEC RTL finds design errors that other tools miss by formally comparing the functionality of the original RTL design and the corresponding optimized RTL design for all possible input sequences. Unlike combinational equivalence checkers, SLEC RTL does not require one to one mapping of registers. SLEC RTL is ideal for verifying RTL changes for retiming and clock gating, allowing designers to confidently make complex changes to their RTL to meet today’s aggressive power and performance design goals.

SLEC Pro provides efficient, comprehensive verification of PowerPro optimized RTL. SLEC Pro formally compares the functionality of the original RTL design with the PowerPro optimized RTL design for all possible input sequences. Unlike combinational equivalence checkers, SLEC Pro does not require one to one mapping of registers.


Message from the Chief Executive Officer (continued)

DAC 2010 promises to be a great event for Calypto.  We will have customer demonstrations of all of our products including our award winning PowerPro MG solution.  We will also demonstrate how our PowerAdviser flow ensures designers are able to achieve the lowest SoC design power possible.  You can sign up for a demonstration at

I hope you find this latest issue of the Calypto Newsletter to be helpful in understanding Calypto's products and capabilities. The newsletter contains the most recent articles and news from Calypto and our partners. Please contact us at: with any questions or comments.

Best Regards,

Tom Sandoval
Chief Executive Officer
Calypto Design Systems

Visit Calypto at DAC in Booth #286

Calypto will be demonstrating its SLEC and PowerPro products at the 47th Design Automation Conference.

DAC 47

Register today for a private demo at:

See Calypto at the following DAC events:

THEATER PRESENTATION - "Next Generation EDA" Monday, June 14th at 3pm in Cadence booth #1334

USER TRACK - “RTL Power Optimization in Sequential Analysis Platforms” Thursday, June 17th at 1:30pm in room 208AB

PANEL - What input language is the best choice for high level synthesis?” Thursday, June 17th at 4:30pm in room 207AB


In This Issue:

Calypto is now on Twitter! Calypto is now on Twitter!


What's New in PowerPro®4.0

PowerPro 4.0 was released on June 1, 2010. This release includes several new enhancements and features including:

  • Improved runtimes by up to 2X with the new enable expression optimization and switching activity propagation capabilities in PowerPro CG.
  • New mode-based optimizations in PowerPro CG enable the tool to implement additional sequential clock gating for maximum power savings.
  • Advancements in PowerPro MG allow users to easily identify memory BIST and ECC logic to the tool, enabling PowerPro MG to find additional memory gating opportunities that can deliver up to 50 percent additional power savings. 
  • Enchanced version of PowerPro Analyzer delivers more accurate power analysis based on new sequential analysis techniques to accurately propagate switching activity. 

For a complete list of features and enhancements, please check the release notes or user’s manual included in the software release package.

WHITEPAPER: PowerAdviser - Empowering Designers with Sequential Power Optimization Opportunities

In power-sensitive products, SoC designers may spend a significant portion of their time looking for ways to optimize their code to dissipate less power during the device’s operation. PowerProCG provides an automated solution to reduce this part of the design time to essentially cut it down to just machine runtime per block. In this paper, we describe a flow that enables two use models; one is to enable the use of PowerPro for designers who must meet very aggressive performance goals and would therefore prefer to optimize their RTL manually, and the other is to enable users of the automated PowerProCG flows to get even better results by providing hints based on sequential analysis. This flow, available within the PowerPro product, is known as PowerAdviser.

Read more>>


SLEC® Tips & Tricks


Debugging Problem Setup Issues

In some cases SLEC will find a falsification where the source of the difference is not due to any design differences but is caused by an incorrect problem setup. The problem setup includes everything which is used to specify how the designs are to be verified:

  • Design parameters values: throughput, latency and reset length.
  • Constraints: used to define the operation of reset or used to constrain only certain modes of operation.
  • Transactors: design elements instantiated to define complex constraints such as one-hot to some encoded state.
  • Blackboxes: internal blocks which may be removed from the analysis.

If the problem setup has not been specified correctly, the two designs may be analyzed in different modes of operations with no chance of them being equivalent or with values of throughput or latency, for example, which are different from the actual design behavior, again ensuring a falsification.

This article explains how to quickly verify the problem setup is correct.

The first indication that the issue may be related to problem setup is typically that the design falsifies during simulation based validation (SBV). Before the formal solvers are used, SLEC performs analysis using the SBV engine (unless it is explicitly disabled). If a falsification is found during SBV it typically means it was an easy problem to find or that there is an issue with the problem setup, since issues with problem setup tend to manifest themselves quickly: the two designs begin to behave differently after only a few cycles.

When the formal solvers begin their analysis, SLEC outputs the following message: “Started sequential analysis”. Even if a design difference is found by the formal solvers it could still be a problem setup issue and the following steps are good first steps in any debug process.

Review the log files.

  • mapping.log: ensure all the inputs are correctly mapped. If the input port names are different in each design they will need to be explicitly mapped to ensure both designs are driven by the same data. Some inputs may require a map with latency, for cases where one design expects the same input N cycles after the other (with respect to the end of reset).

  • bbox.log: confirm both designs have the same blocks specified as blackboxes or that one of designs correctly has additional functionality removed by blackboxing.

  • ccheck_spec.log, ccheck_impl.log and reset.log: review these files to confirm there are no sources of unknown (‘hX) values such as un-driven input pins or flops which start as unknown and propagate unknown values (‘hX) into the design. Review the SLEC User Guide for special handling of unknown (‘hX ) values in the design.

A useful technique before proceeding to check the design setup parameters is to enable the SLEC auxiliary signals. The auxiliary signals are written to the VCD files and show when SLEC applies the 1st , 2nd, 3rd, etc. input values to each input port and checks the corresponding 1st, 2nd, 3rd, etc. output values of each output port. In cases where the designs have different throughputs or latencies, the auxiliary signals significantly help with the ability to align the waveforms of the two designs for detailed analysis.

  • If the designs are cycle accurate with a throughput of one, such as in an RTL-to-RTL comparison, the following check can be ignored. Check any internal state elements which are affected only by the clock or reset (no other inputs, even via internal signals, affect their operation or behavior). Good candidates are state/FSM vectors, counters, output or input handshakes. Adjust the throughput to ensure these elements repeat every transaction (as defined by the throughput) and return to the same state at the start of each transaction.

  • Verify the reset length for both designs is correct. The auxiliary signal trans_start shows when the first input data is applied on the input ports. This is done at the end of the specified (or default) reset phase. If one design requires for example 4 clocks before it is ready to accept an input, specify the reset length as 4, or the inputs will be applied too early, ensuring a difference in behavior.

  • Confirm that the latency specified for each design, or specified individually for each port, is correct. The auxiliary signals can be used to compare one design with another. For example, the 1st output for each port will be compared when the associated (by name) auxiliary signal has the value 1. The 2nd output compared when the auxiliary signal has value 2 etc.

  • If transactors are used at the input and output, confirm the data is being correctly transformed by the transactor: check the waveforms at both the inputs and outputs of the transactor.

If the above items appear correct, it is likely the falsification is due to a genuine design difference and a more focused detailed debug effort may be required to determine the exact nature of the difference.




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