Calypto Newsletter |
April 2009 Issue |
Message from the Chief Executive OfficerWelcome to the Spring 2009 edition of the Calypto Newsletter where you will find the latest news and information about Calypto and our market leading products. This issue includes several interesting articles covering the capabilities of PowerPro™ CG and SLEC® products. PowerPro CG use continues to expand through new customers and through the broader deployment of PowerPro CG at existing customers where the tool has been fully integrated into the RTL/Synthesis design process. With automated flows for verification and ECOs, customers have proven that PowerPro CG fits seamlessly into their RTL implementation methodology. The power savings provided by PowerPro CG has been confirmed on hundreds of designs through place and route. SLEC continues to show its value in both the ESL and RTL flows. SLEC System is being used by customers as part of their standard verification regression methodology as they develop and refine their RTL design using their C model as the golden reference. Meanwhile, SLEC System-HLS has uncovered bugs in customer designs associated with fixed point saturation and integer overflow. What's New in SLEC® 3.3SLEC® version 3.3 was released on March 16th 2009. The latest version of SLEC contains the following features and enhancements:
These new capabilities further reinforce SLEC’s position as the cornerstone of today's advanced high-level synthesis (HLS) design flows. Users should move to SLEC 3.3 as soon as possible. Power Optimization of a Configurable Video Platform using PowerPro™ CGWith the proliferation of mobile multimedia devices, providing the most advanced features to the user is always a challenge when it has to be balanced against battery life. One way to reduce power and extend battery life is to reduce the amount of switching activity in the device. Understanding how the silicon works in normal use can help direct subsystem design changes to eliminate unnecessary switching activity without sacrificing leading edge functionality and performance. Once identified, the challenge is to quickly and efficiently implement the changes in the RTL and be able to verify that the functionality has not been affected by the changes. Clock gating is one common Register Transfer Level (RTL) power optimization technique that reduces design switching activity. It relies on the ability of synthesis tools to identify certain RTL structures and convert those structures into simple combinational clock gating logic. Until recently, inserting these structures into RTL was a tedious, error-prone, manual process. Verification of the structures required the creation of new test benches to ensure that the changes to the design did not affect functionality. With the advent of RTL power optimization and verification tools, the process has become automated, providing an ideal solution for reducing power in highly configurable SoC subsystems used in today’s mobile multimedia devices. PowerPro™ CG is an automated power optimization tool that inserts advanced sequential clock gating structures into an RTL design. PowerPro CG is based on Calypto’s patented Sequential Analysis Technology, and is proven to reduce power by up to 60% on customer designs. PowerPro CG evaluates circuit behavior across multiple clock cycles to identify sequential clock gating enable conditions and generates new RTL which is identical to the original RTL with new clock gating enable logic inserted. All user defined pragmas, indentations, comments, etc. are maintained. Designers feel comfortable with the generated RTL because they can still recognize their original coding style and are provided direct insight into the logic inserted by PowerPro CG. SLEC® CG is a sequential equivalence checker that provides efficient, comprehensive verification of the PowerPro CG generated RTL. SLEC CG formally compares the functionality of the original RTL design with the PowerPro CG optimized RTL design for all possible input sequences to ensure functionality has not been compromised. Read more>>
Calypto in the News03/25/09 EDA Confidential - Reaching the EDA Customer 03/07/09 EDA Cafe - Is EDA History? Is it Doomed? 01/23/09 SOCcentral - ARC, Calypto Team to Reduce Power in ARC's Video Subsystem Solution 01/15/09 DACeZine -Leveraging System Models for RTL Functional Verification using Sequential Logic Equivalence Checking 01/12/09 EDA Cafe - Sequential Analysis
Product Information PowerPro™ CG SLEC®
System SLEC®
System-HLS SLEC®
RTL SLEC®
CG SLEC ® Tips & Tricks (continued)The CALYPTO_SYSC define is auto-defined when SLEC reads any C design and ensures the additional code is only recognized by SLEC. #ifdef CALYPTO_SYSC #include "calypto_debug.h" #endif in_val = in_port1.read(); sum_val = in_port2.read(); for (int i = 0 ; i < 10; i++) { foo(in_val, sum_val, out_val, out_scale); #ifdef CALYPTO_SYSC calypto_cout("sum_val", sum_val); #endif if (i>5) { sum_val = sum_val + out_val; } else { sum_val = sum_val * out_scale; } } out_port1.write(sum_val); The VCD traces files generated by SLEC in the presence of a difference will contain signals __Calypto_cout__sum_val_0 to __Calypto_cout__sum_val_9 which respectively show the value of sum_val in loop iterations 0 to 9. The corresponding waveform in the RTL will be the output of the function which is the RTL sub-block foo. The calypto_cout function can be extended to capture other signals of interest (out_val, out_scale etc.) and at any level of hierarchy (e.g. inside function foo). Each signal is given a unique identifier number based on when the signal was first assigned a value. When multiple calypto_cout functions are used in conditional branches, this intuitively shows how the code is being executed. Even for cases with highly optimized RTL such as those produced by High Level Synthesis (HLS) tools, certain points in the C code always lend themselves to corresponding points in the RTL. For Example: C function outputs and RTL sub-block outputs, the output of adders and multipliers, other macro level IP components. A recommended methodology would be: 1) Include "calypto_debug.h" in the C design. 2) Add one or more calypto_cout functions to the C code. 3) Add "set_global prune_unmapped_logic 0" to the SLEC Tcl file 4) Run SLEC to get a falsification. 5) Type “view_waveform” in SLEC and both the C and RTL waveforms will be displayed in SpringSoft’s Verdi/Debussy or open the VCDs using your standard VCD viewer. 6) If more detail is required, add more calypto_cout functions to the C code 7) Repeat from step 4 until the falsification is resolved
Message from the Chief Executive Officer (continued)SLEC RTL is being used by customers to efficiently produce the lowest power, highest performance RTL by enabling the implementation of sequential design modifications such as re-pipelining and clock gating. SLEC RTL provides comprehensive functional verification of these design modifications to ensure the optimized RTL is functionally equivalent to the original RTL. I hope you find this latest issue of the Calypto Newsletter to be helpful in understanding Calypto's products and capabilities.
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What's New in PowerPro™ CG 2.2PowerPro™ CG 2.2 was released on April 15, 2009. This release includes several new enhancements and features including:
For a complete list of features and enhancements, check out the release notes or user’s manual included in the software release package. SLEC ® Tips & TricksFAST DEBUG OF C DESIGNS When any verification procedure finds a difference between a C model and the RTL implementation of that model, the design must be analyzed to determine what is causing the difference. The key to performing this debug operation efficiently is the ability to easily compare the simulation results from the C model with the simulation results of the RTL. In some small examples, it may be possible to determine the difference by examining the top-level IO signals, but with increasingly complex C models being used in today’s designs, this is becoming more and more difficult. The following example highlights one of the main challenges in debugging the differences and presents a highly efficient solution. This snippet of C code performs a “simple calculation in a loop”. After reading two inputs, a for-loop performs function foo, the output of which will affect the next input to function foo. SystemC semantics are used here to make it clear what the top-level input reads and output writes are: the same debug problem will exist in a standard C/C++ design. in_val = in_port1.read(); sum_val = in_port2.read(); for (int i = 0 ; i < 10; i++) { foo(in_val, sum_val, out_val, out_scale); if (i>5) { sum_val = sum_val + out_val; } else { sum_val = sum_val * out_scale; } } out_port1.write(sum_val); Given the same inputs to both models but a different output value, the difference in the outputs can be easily determined by confirming in which iteration of the for-loop the RTL model output is different from the output of the C model. However, C designs execute in zero time and the intermediate values of sum_val are lost. Adding printf statements to the C will permit these intermediate values to be captured. However, this requires comparing text output against RTL waveforms and the printf statements will require some notion of time, transaction number, loop iteration number or some combination of them to productively match up the text to the waveforms. The SLEC calypto_cout feature allows the intermediate values of any C model to be captured as waveforms and compared side-by-side with the RTL waveforms. With the changes to the code shown below, and by adding “set_global prune_unmapped_logic 0” to the SLEC Tcl file, SLEC will capture the value of sum_val in each loop iteration as a unique output waveform. This waveform can be easily compared to the waveform of the RTL design.
Read more >>PowerPro™ CG Tips & TricksVHDL Auto Black-boxing To facilitate VHDL black boxing (black boxing of verilog modules instantiated in VHDL design), PowerPro CG can write out shells by looking into the component declarations which can later be read as dummy interfaces and create black boxes around them. This avoids auto inference of port direction and types in VHDL. Command and usage: write_vhdl_shell -output_dir <output_dir_name> [-spec | -impl | -work] [-top < top_unit >] -output_dir <output_dir_name> The name of the directory in which shell files will be generated. -spec | -impl | -work Optional flags to specify the library for which shells are required to be generated. Default is -work -top < top_unit > Optional flag to specify the top unit name of the design. If this option is not provided, PowerPro CG will use the same rule to detect the top module as is used by build_design. Internally, write_vhdl_shell will perform the following 3 steps: 1) Elaborate the top design unit to locate the black box component declaration 2) Generate the black box shells 3) Clear the existing design from the tool The side effect of the 1st and 3rd step is that; 1) After write_vhdl_shell, the user will have to re-read the original design and then read the dummy shells generated before link_design can be performed. 2) Write_vhdl_shell cannot be called more than once without re-reading the design. An example usage in the PowerPro flow would be: Step 1: Apply create_black_box in all the verilog modules. create_black_box –module vlog_mod1 create_black_box –module vlog_mod2 # etc Note: If the above step is not done, PowerPro CG will error out during the link_design command execution and create the file create_bbox.tcl inside the work directory. That file is then used to apply create_black_box in all verilog modules. Step 2: Read in all the VHDL files in any order. read_design mid1.vhd read_design top.vhd read_design mid2.vhd Step 3: Execute “write_vhdl_shell” command to create a VHDL shell for black-boxed Verilog modules. write_vhdl_shell –-top top –output_dir bbox_dir Step 4: Finally, read all previously read VHDL files again with the file generated in step 3. After that execute remaining downstream PowerPro CG commands. read_design top.vhd #Reading again read_design mid1.vhd #Reading again read_design mid2.vhd #Reading again read_design bbox_dir/vlog_mod1.vhd #Reading the file generated in Step3 read_design bbox_dir/vlog_mod2.vhd #Reading the file generated in Step3 link_design -top top build_db prototype_design Please note that you don't need to exit the tool to re-read the design, but the same files have to be read in the same run. However, Step 2 and 3 is only for the first time the design is read because once VHDL shells have been generated, the user only needs to execute steps 1 and 4 for subsequent PowerPro CG runs. |
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