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Benefits of SLEC System-HLS

  • Independent verification of high level synthesis results
  • Reduces project risk by identifying ambiguities between system and RTL languages
  • Verifies RTL blocks without waiting for the entire assembled design
  • Supports Forte Modular Interfaces and Mentor Algorithm CTM datatypes
  • Replaces time consuming simulation regressions with fast results
  • Isolates bugs quickly with short, concise debug waveforms

SLEC System-HLS comprehensively verifies the RTL generated by High Level Synthesis (HLS) tools.

Based on Calypto’s patented Sequential Analysis Technology, SLEC System-HLS eliminates functional errors in High Level Synthesis (HLS) generated RTL.

SLEC System-HLS finds design errors that other tools miss by formally comparing the functionality of a system level model written for HLS with its corresponding synthesized RTL design across all possible input sequences. Unlike combinational equivalence checkers, SLEC System-HLS does not require one to one mapping of registers. SLEC System-HLS increases design productivity through automated setup and elimination of block-level RTL simulation.

SLEC System-HLS either confirms that no functional errors exist or generates short, concise waveforms that pinpoint design bugs. These waveforms are written in standard VCD and FSDB formats that can be analyzed in the user’s native debugging environment.

SLEC System-HLS is part of Calypto’s SLEC family of proven sequential equivalence checking products. SLEC System-HLS provides a seamless link with Cadence, Mentor and Forte HLS tools and requires a SLEC System license.