Calypto Quarterly Newsletter

Calypto Newsletter

March 2010 Issue

Message from the Chief Executive Officer

It’s hard to believe that I am writing for the Spring 2010 edition of the Calypto Newsletter, amazing how time flies.  This issue includes several articles covering the capabilities of our PowerPro® and SLEC® product families. 

The beginning of this year has been very exciting for Calypto.   We had record bookings and revenues for our Q3 (ended Jan. 31), and in early February, EDN informed us that our PowerPro MG product is a finalist in the EDN Innovations Award in the “EDA: Front-End Analysis and Synthesis Tools” category.   One winner will be determined from among the finalists through votes cast on the EDN website.  We encourage you to vote today at:  Voting runs through March 19th, 2010.  Winners will be announced on April 26th at the EDN awards ceremony in San Jose, CA.  Our PowerPro CG product was a finalist in 2008.  We need your help to make PowerPro MG the final award winner in 2010.

So why should you vote for PowerPro MG?  If you are concerned about power in your SoC design, it is reasonably obvious.  Up to 70% of power in an SoC design is due to power dissipation in on-chip memories, and PowerPro MG is the only tool available that automatically reduces on-chip memory power. 

Similar to PowerPro CG, PowerPro MG fits seamlessly into today’s RTL synthesis flows.  The tool reads in an RTL design as well as the applicable memory models.  Using Calypto’s patented Sequential Analysis Technology, the tool constructs new memory gating logic that works in conjunction with the low-power memory modes to reduce both static and dynamic on-chip memory power.   PowerPro MG then generates new power-optimized RTL that looks identical to the original RTL except for the addition of the new memory gating logic. 


What's New in SLEC® 4.1

SLEC® version 4.1 was released on December 17, 2009. The latest version of SLEC contains the following features and enhancements:

  • Several improvements in the performance of the full-proof engines. These improvements enable SLEC to achieve full-proofs in several cases in HLS-flows and RTL-RTL verification.
  • Significant advancements in the Mentor Catapult, Forte Cynthesizer and Cadence C-to-Silicon integrations.
  • Enhancements in the handling of C++/SystemC designs which results in significant performance improvements in build_design for larger designs. In some customer cases, a 3X reduction in peak-memory usage and 2X reduction in elaborationtime was observed.
  • Improvements in word-level solvers for designs with fixed-point datatypes i.e. ac_fixed datatypes in Catapult flows and cynw_fixed datatypes in Cynthesizer flows.

These new capabilities further reinforce SLEC’s position as the cornerstone of today's advanced high-level synthesis (HLS) design flows. Users should move to SLEC 4.1 as soon as possible.

Calypto in the News

02/22/10 Calypto’s PowerPro MG Named a Finalist in 20th Annual EDN Innovation Awards: A prestigious honor for the industry’s only automated memory power optimization tool

02/01/10 Virage Logic’s 45nm and 28nm SiWare Memory Compilers Automatically Support Calypto’s PowerPro MG tool; Compilers automatically generate PowerPro MG views to fully automate on-chip memory power optimization (Japanese version)

01/19/10 Chip Design - Calypto PowerAdviser Flow Optimizes SoCs

01/19/10 EDN - Calypto to power-management experts: have it your way

12/16/09 Calypto’s PowerPro MG Named ‘Best of 2009’ by Electronic Design (Japanese version)

12/01/09 Electronic Design - ESL Tools Take Center Stage as Designers Move Up

10/15/09 EDA DesignLine - How to Reduce Memory Power in SoC Designs


PowerPro® Tips & Tricks

Using Powerpro with mode constraints

Often designs operate in various modes controlled by pins such as SCAN, BIST, ATPG, etc. or by configuration register bits. These modes exist in order to implement all the functional aspects of the design and to verify the correctness of the design.  Typically, in the normal mode of the design operation (mode of interest for power optimizations), the signals controlling other modes are set to their inactive values.  PowerPro can safely make use of the information about inactive signals to optimize the design to further reduce power. Since such information about these pins is not available in the RTL description of the design, PowerPro provides the ability for a user to specify mode-specific constraints on such pins. Once PowerPro sees the constraints, it automatically performs optimizations specific to those constraints and also generates override logic to disable these optimizations when the design is not running with those mode-specific constraints. This enables PowerPro to automatically reduce power on the design.

Consider the following design scenario for a multi-media block that can process audio as well as video.


In the normal operation of this block, Test_Mode is always set to zero and TOP_BLOCK works as an audio processor whenever Video_Mode is set to zero.   Otherwise, it works as a video processor. The designer has already incorporated coarse level clock gating so that AUDIO_BLOCK is shut off when “Video_Mode == 0” and VIDEO_BLOCK is shut off when “Video_Mode == 1”.

Using PowerPro’s ability to understand modes, PowerPro automatically performs optimizations using the user defined mode constraints and also ensures that the mode-specific optimizations are turned off when the constraints are not applicable.

The following command can be used to create a mode, called ACTIVE:


     create_mode  –name ACTIVE 

Multiple ports/signals can then be constrained to define inactive values for the mode. The signals to be constrained are Test_Mode and Video_Mode. The following commands constrain these signals for ACTIVE mode.


create_mode_constraint –mode ACTIVE  –module TOP_BLOCK –value 0 
   –signal Test_Mode
create_mode_constraint –mode ACTIVE –module AUDIO_BLOCK –value 0 
  –signal  Video_Mode     
create_mode_constraint –mode  ACTIVE –module VIDEO_BLOCK –value 1 
  –signal Video_Mode 

NOTE: At present, PowerPro allows the creation of only one mode and will error out if create_mode is issued multiple times. The user can then constrain multiple ports/signals to specific constant values under this mode

SLEC® Tips & Tricks (continued)

The CALYPTO_SYSC define is auto-defined when SLEC reads any C design and ensures the additional code is only recognized by SLEC.

  #ifdef  CALYPTO_SYSC 
  #include  "calypto_debug.h"
  in_val =;
  sum_val =;
  for (int i = 0 ; i < 10; i++)
  foo(in_val, sum_val, out_val, out_scale);
  #ifdef CALYPTO_SYSC 
  calypto_cout("sum_val", sum_val);
  if (i>5) {
  sum_val = sum_val + out_val;
  } else {
  sum_val = sum_val * out_scale;

The VCD traces files generated by SLEC in the presence of a difference will contain signals __Calypto_cout__sum_val_0 to __Calypto_cout__sum_val_9 which respectively show the value of sum_val in loop iterations 0 to 9. The corresponding waveform in the RTL will be the output of the function which is the RTL sub-block foo.

The calypto_cout function can be extended to capture other signals of interest (out_val, out_scale etc.) and at any level of hierarchy (e.g. inside function foo). Each signal is given a unique identifier number based on when the signal was first assigned a value. When multiple calypto_cout functions are used in conditional branches, this intuitively shows how the code is being executed.

Even for cases with highly optimized RTL such as those produced by High Level Synthesis (HLS) tools, certain points in the C code always lend themselves to corresponding points in the RTL.  For Example: C function outputs and RTL sub-block outputs, the output of adders and multipliers, other macro level IP components.

A recommended methodology would be:

  1. Include "calypto_debug.h" in the C design.
  2. Add one or more calypto_cout functions to the C code.
  3. Add "set_global prune_unmapped_logic 0" to the SLEC Tcl file
  4. Run SLEC to get a falsification.
  5. Type “view_waveform” in SLEC and both the C and RTL waveforms will be displayed in SpringSoft’s Verdi/Debussy or open the VCDs using your standard VCD viewer.
  6. If more detail is required, add more calypto_cout functions to the C code
  7. Repeat from step 4 until the falsification is resolved

Message from the Chief Executive Officer (continued)

We have collaborated very closely with Virage Logic, the leader in low-power, high-performance memory IP, on this product.  As a result, Virage Logic’s SiWare™ memory compilers for 45nm and 28nm automatically generate PowerPro MG power optimization models for reducing SoC on-chip memory power. 

The results speak for themselves:


We continue to make significant advances in our PowerPro CG product.  In January, we introduced our new PowerAdviser Flow.  Using sequential design information generated by PowerPro, the PowerAdvisor flow provides users with specific design changes that can be manually implemented in their RTL code to reduce power.  The PowerAdviser Flow presents design optimizations in the form of RTL changes, schematics, and textual descriptions.  Many design teams are using this capability today to deliver unparalleled results.

Our SLEC System-HLS product continues to be a key part of ESL flows for customers worldwide.  We are working closely with our partners—Cadence, Mentor, and Forte—to ensure we provide an easy to use methodology for delivering comprehensive, formal verification for HLS generated RTL.

I hope you find this latest issue of the Calypto Newsletter to be helpful in understanding Calypto's products and capabilities. The newsletter contains the most recent articles and news from Calypto and our partners. Please contact us at: with any questions or comments...and vote today at for PowerPro MG!

Best Regards,

Tom Sandoval
Chief Executive Officer
Calypto Design Systems

Vote for PowerPro MG in the EDN Innovation Awards competition!

In This Issue:

Calypto is now on Twitter! Calypto is now on Twitter!

What's New in PowerPro® 3.1

PowerPro 3.1 was released on December 18, 2009. This release includes several new enhancements and features including:

  • The new PowerAdviser flow which produces additional information to assist the designer with obtaining maximum power savings.
  • Enhanced support for memory gating optimization to automatically identify and generate memory enable and power mode controls to reduce dynamic and leakage power on memories, available in PowerPro MG.
  • Several new and more powerful observability and stability based optimizations have been provided to achieve more power savings including slicing of large flop banks and enhanced check for detecting gating conditions of a flop.
  • Advanced support for ECO of observability as well as stability based power optimization.

For a complete list of features and enhancements, please check the release notes or user’s manual included in the software release package.

NEW white paper: PowerAdviser - Empowering Designers with Sequential Power Optimization Opportunities

In power-sensitive products, SoC designers may spend a significant portion of their time looking for ways to optimize their code to dissipate less power during the device’s operation. PowerProCG provides an automated solution to reduce this part of the design time to essentially cut it down to just machine runtime per block. In this paper, we describe a flow that enables two use models; one is to enable the use of PowerPro for designers who must meet very aggressive performance goals and would therefore prefer to optimize their RTL manually, and the other is to enable users of the automated PowerProCG flows to get even better results by providing hints based on sequential analysis. This flow, available within the PowerPro product, is known as PowerAdviser.

Read more>>


SLEC® Tips & Tricks



When any verification procedure finds a difference between a C model and the RTL implementation of that model, the design must be analyzed to determine what is causing the difference. The key to performing this debug operation efficiently is the ability to easily compare the simulation results from the C model with the simulation results of the RTL. In some small examples, it may be possible to determine the difference by examining the top-level IO signals, but with increasingly complex C models being used in today’s designs, this is becoming more and more difficult. The following example highlights one of the main challenges in debugging the differences and presents a highly efficient solution.

This snippet of C code performs a “simple calculation in a loop”. After reading two inputs, a for-loop performs function foo, the output of which will affect the next input to function foo. SystemC semantics are used here to make it clear what the top-level input reads and output writes are: the same debug problem will exist in a standard C/C++ design.

  in_val =;
  sum_val =;
  for (int i = 0 ; i < 10; i++)
  foo(in_val, sum_val, out_val, out_scale);
  if (i>5) {
  sum_val = sum_val + out_val;
  } else {
  sum_val = sum_val * out_scale;

Given the same inputs to both models but a different output value, the difference in the outputs can be easily determined by confirming in which iteration of the for-loop the RTL model output is different from the output of the C model. However, C designs execute in zero time and the intermediate values of sum_val are lost.

Adding printf statements to the C will permit these intermediate values to be captured.  However, this requires comparing text output against RTL waveforms and the printf statements will require some notion of time, transaction number, loop iteration number or some combination of them to productively match up the text to the waveforms.

The SLEC calypto_cout feature allows the intermediate values of any C model to be captured as waveforms and compared side-by-side with the RTL waveforms. With the changes to the code shown below, and by adding “set_global prune_unmapped_logic 0” to the SLEC Tcl file, SLEC will capture the value of sum_val in each loop iteration as a unique output waveform.  This waveform can be easily compared to the waveform of the RTL design.


Product Information

PowerPro® MG
PowerPro MG is an automated memory power optimization solution that takes advantage of the low-power control options available in today’s on-chip memories to reduce both dynamic and leakage memory power with little or no impact to timing or area. PowerPro MG reduces dynamic power by automatically generating logic to control the memory enable signal to eliminate unnecessary memory accesses. 

PowerPro® CG
Based on Calypto’s patented Sequential Analysis Technology, PowerPro CG reduces power by up to 60% in RTL designs. PowerPro CG evaluates circuit behavior across multiple clock cycles to identify sequential clock gating enable conditions. New enable logic is inserted into the original RTL code while maintaining all user defined pragmas and comments.

PowerPro® Analyzer
PowerPro Analyzer is the industry’s most accurate register-transfer level (RTL) power analysis tool. PowerPro Analyzer performs sequential analysis of the entire design, delivering power measurement results that are significantly more accurate than the decade-old RTL power analysis tools in use today.

PowerAdviser Flow

The PowerAdviser Flow provides designers with a flow for manually modifying RTL code during design creation to achieve the lowest power dissipation possible using design and power information generated by PowerPro.


SLEC® System
Enabling ESL
SLEC System finds design errors that other tools miss by formally comparing the functionality of an Electronic System Level (ESL) model written in C/C++/SystemC with its corresponding RTL design or system-level model for all possible input sequences. Unlike combinational equivalence checkers, SLEC System does not require one to one mapping of registers. The quality of verification SLEC System performs in minutes is equal to months of running simulation.

SLEC® System-HLS
SLEC System-HLS finds design errors that other tools miss by formally comparing the functionality of a system level model written for HLS with its corresponding synthesized RTL design across all possible input sequences. SLEC System-HLS increases design productivity through automated setup and elimination of block-level RTL simulation.

SLEC RTL finds design errors that other tools miss by formally comparing the functionality of the original RTL design and the corresponding optimized RTL design for all possible input sequences. Unlike combinational equivalence checkers, SLEC RTL does not require one to one mapping of registers. SLEC RTL is ideal for verifying RTL changes for retiming and clock gating, allowing designers to confidently make complex changes to their RTL to meet today’s aggressive power and performance design goals.

SLEC Pro provides efficient, comprehensive verification of PowerPro optimized RTL. SLEC Pro formally compares the functionality of the original RTL design with the PowerPro optimized RTL design for all possible input sequences. Unlike combinational equivalence checkers, SLEC Pro does not require one to one mapping of registers.



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