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Benefits of PowerPro-filer

  • Gives designers insight into RTL power saving opportunities
  • Generates clock-gating statistics for RTL design blocks
  • Reports the percentage of registers clock gated
  • Uses switching activity to report clock-gating efficiency
  • Guides power optimization efforts

RTL Power Profiling Utility

PowerPro-filer is a Linux utility that calculates Clock-Gating Efficiency as well as the percentage of registers clock gated in a RTL design block.

Clock-Gating Efficiency measures the percentage of time a register is gated (turned off) for a given set of activity vectors.  Since Clock-Gating Efficiency takes into account switching activity, it is a much better indicator of clock gating effectiveness and dynamic power savings. PowerPro-filer reads in synthesizable Verilog RTL and activity vector files (SAIF or VCD) in order to report how well your design is optimized for power.

PowerPro-filer is part of Calypto's PowerPro product family which includes PowerPro CG and PowerPro MG.

PowerPro-filer is available for download FREE of charge.

Reports Clock-gating Efficiency


White Paper

Utilizing Clock-Gating Efficiency to Reduce Power in RTL Designs

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